前瞻网路安全处理器及 相关SOC设计与测试技术研发 C .pptVIP

Transistor-Transistor Logic and BiCMOS Dr. T.Y. Chang NTHU EE 2007.12.11_13 Introduction Diode-Transistor Logic Basic TTL NAND gate Schottky TTL BiCMOS Text Book: D.A. Neamen, Electronic Circuits Analysis And Design, 2nd ed. Chapters 17. Parameters Diode-Transistor Logic Example 17.8 @p1137 Find Is and Vs in DTL as shown in Fig. 17.20 with ? 25. Evolution Multi-Emitter Cross Section TTL Inputs TTL TTL with Totem-Pole Output TTL Layout Fanout Modified Totem-Pole TTL Tristate Output Schottky BJT Schottky TTL Low-Power Schottky TTL Example 17.12 @p1154 Calculate power dissipation in Fig. 17.34 with ? 25, V? 0.7V, VCE sat 0.4V. Advanced Schottky TTL BiCMOS CMOS Low Power Slower BJT Faster High Power Core: CMOS, Interface: BJT Basic BiCMOS Inverter Totem-Pole Configuration Q1-Q2 Turn-off time VOH VDD－VBE ON VOL VBE ON BiCMOS Inverters BiCMOS Inverter I Reduce Turn-off time “bleeder resistors” R1 and R2 are added VOH VDD－VBE ON VOL VBE ON BiCMOS Inverter II Reduce Turn-off time VOH VDD and VOL 0 BiCMOS NAND2 Gate BiCMOS NOR Problem Not HW Implement E AB+CD in two-level TTL gates. Implement a BiCMOS NAND gate. Solutions E AB+CD AB ’ CD ’ ’ * Laboratory of Reliable Computing * Laboratory of Reliable Computing Logic-1 5V Logic-0 0.1V Ex 17.9 Find Is, Vs, and Max. Fanout of Fig. 17.24. ?R 0.1, ? 25. If No Rc ? Called Open-Collector TTL OC TTL Wired-AND: Connects outputs of OC TTLs and adds an Rc 0 switch open 1 switch on 0 1 VBE ON or VDD? VBE ON 0V or VDD