四位全加器的VDL与VerilogHDL实现.docVIP

四位全加器的VHDL/VerilogHDL实现 加法器的分类 （一半加器 信号输入 信号输出 A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 （1）（2）二全加器 信号输入端 信号输出端 Ai Bi Ci Si Ci 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 module add(A,B,CI,CO,S); parameter N=4; input [N:1] A,B; input CI; output CO; output [N:1] S; assign {CO,S}=A+B+CI; endmodule 四位全加器常用三种编程方法： /*module add(s,co,a,b,ci);//行为描述法 output[3:0] s; output co; input[3:0] a,b; input ci; reg co; reg[3:0] s; always@(*) begin {co,s}=a+b+ci; end endmodule*/ module add(s,co,a,b,ci);//结构描述法 output[3:0] s; output co; input[3:0] a,b; input ci; full_add1 f0(a[0],b[0],ci,s[0],ci1); full_add1 f1(a[1],b[1],ci1,s[1],ci2); full_add1 f2(a[2],b[2],ci2,s[2],ci3); full_add1 f3(a[3],b[3],ci3,s[3],co); endmodule module full_add1(a,b,cin,sum,cout); input a,b,cin; output sum,cout; wire s1,m1,m2,m3; and(m1,a,b), (m2,b,cin), (m3,a,cin); xor(s1,a,b), (sum,s1,cin); or(cout,m1,m2,m3); endmodule /*module add(co,s,a,b,ci);//数据流法 output[3:0] s; output co; input[3:0] a,b; input ci; assign {co,s}=a+b+ci; endmodule*/ appearance of the weld appearance quality technical requirements of the project must not have a molten metal stream does not melt the base metal to weld, weld seam and heat-affected zone surface must not have cracks, pores, defects such as crater and ash, surface smoothing, weld and base metal should be evenly smooth transition. Width 2-3 mm from the edge of weld Groove. Surface reinforcement should be less than or equal to 1 + 0.2 times the slope edge width, and should not be greater than 4 mm. Depth of undercut should be less than or equal to 0.5 mm, total length of the welds on both sides undercut not exceed 10% of the weld length, and long continuous should not be greater than 100 mm. Wrong side should be less than or at 0.2T, and should not be greater than 2 mm (wall thickness mm t) incomplete or not allow 7.5 7.5.1 ins