EDA第三章 icrosoft Word 文档.docVIP

s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE one OF mux21 IS BEGIN PROCESS ( s0,s1,a,b,c,d ) BEGIN IF s1=’0’ AND s0=’0’ THEN y=a ; ELSIF s1=’0’AND s0=’1’ THEN y=b ; ELSIF s1=’1’AND s0=’0’ THEN y=c ; ELSIF s1=’1’AND s0=’1’ THEN y=d ; ELSE y=NULL ; END IF ; END PROCESS ; END ARCHITECTURE one ; CASE 语句 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 IS PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE two OF mux21 IS SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 )