(ppt)EDA第7章VHDL顺序语句(program).pptVIP

第6章 VHDL顺序语句 library ieee; use ieee.std_logic_1164.all; entity reset_dff2 is port( clk,reset : in std_logic; d : in std_logic; q : out std_logic); end reset_dff2; architecture rtl of reset_dff2 is begin process begin wait on clk, reset; if (reset = ‘1’ ) then q = ‘0’; elsif（clk’event and clk=‘1’) then q = d; end if; wait on clk, reset; end process; end rtl; process begin wait until clk’event and clk=‘1’； if (reset = ‘1’ ) then q =