4-1定理chenyu案例.pptVIP

Exercise before class： 【Exercise 1】Which The maximum?propagation delay?of the 74LS00?is tpLH = tpHL=15ns. For both LOW-HIGH and HIGH-LOW transitions, determine the exact maximum propagation delay from IN?to OUT of he?below?circuit.? (Every?gate?uses?the?worst case?of?delay to calculate). Exercise before class： 【Exercise 2】Which logic gate of the following CMOS gates is corresponding to in the sense of negative logic? (1）AND (2)OR (3)NAND (4)NOR 【Solution】(1)OR (2) AND (3)NOR (4)NAND c h a p t e r 4 Combinational Logic Design Principles c h a p t e r 4 Switching Alge