VHDL的ASIC实现_前端概要.pptVIP

* * * * * * * * * 5. 建立约束 设定优化约束 Design Constraints ... Max area : 0 to get the min. area Timing constraints ... Combinational Circuit : Select the in/out pin which you want to specify Attributes - Optimization Constraints - Timing Constraints Sepcicy your target and then press “Ok” Sequential Circuit : Select clock pin “clk” Attributes - Specify Clock ... Period : 12 , Rising : 0, Falling : 6 Press “Ok” 6. 编译设计 Choose Design Compile Design. Map effort : medium Area effort : medium Click “Ok” to begin compiling. 7. 保存设计 File - Save info - Design Setup ( your_design.dc) save all your design constraints, you may load it : File - Ececute Script ... File - Save info - Design Timing (your_design.sdf) Save delay timing information with Standard Delay Format v1.0. It will be referenced during gate level simuation. `include MLMS1.gv `include umc18.v module test_MLMS1_gv(); parameter ADC_bits = 4, W1_bits = 16, M = 40, step_size = -8; reg clk,rst; reg [ADC_bits*M-1:0] x; reg [ADC_bits-1:0] mem [40000:0]; reg [ADC_bits-1:0] temp; reg signed [W1_bits-1:0] temp2; wire [M-1:0] y; wire [W1_bits*M-1:0] e; MLMS1 u1(clk,rst,x,y,e); always #8 clk = ~clk; initial begin $readmemh(test_MLMS1.dat,mem); fid = $fopen(MLMS1_result_gv.dat); $fsdbDumpvars; $fsdbDumpfile(MLMS1_gv.fsdb); $sdf_annotate(MLMS1.sdf,u1); ... File - Save as - select Format (Verilog) Save synthesis result .... (your_design.v) or (your_design.gv) you should include your_design.gv and your_design.sdf in your test file. 8. 生成报告 Timing 1. Select Top in the logical hierarchy view. 2. Choose Timing Report Timing Paths 3. Click “Ok” Note: Slack is defined as the time difference between the timing goal for a path and its actual timing. Paths that meet the design’s timing goals have positive slack values Worst Slack Timing Report ... u81/WW1[14]