基于FPGA的HDLC協议设计.docxVIP

摘要 高级数据链路控制(HDLC)协议是数字通信中的重要协议之一。Altera公司的可编程门阵列(FPGA)，设计了一种基于并行机制的高级数据链路控制(HDLC)协议控制系统。该系统采用模块组合的设计方法，使系统的复杂功能由各个模块组合实现，这种分块处理使得设计层次清晰且易于修改。该系统有效利用FPGA的内部硬件资源，实现了并行的多通道的HDLC协议报文的生成和解析。通过分析当前实现HDLC协议的一般方法，指出其存在的一些弊端，提出了一种利用FPGA编程实现HDLC协议的硬件处理方法，并对FPGA如何实现HDLC协议的帧序列校验——循环冗余校验(CRC)进行了阐述。模块下载到硬件中测试通过，证实了FPGA实现HDLC协议的可行性，模块编程简单且易于修改使其在应用中具有很大的优越性。基于在数据通信中为了降低通信线路传输的误码率，需要采用高效能的差错控制方法。循环冗余校验ＣＲＣ由于编码简单且有效，是一种最常用的信道编码方。 【关键词】：HDLC协议　　　FPGA　　CRC校验 　　 ABSTRACT High level data link control (HDLC) protocol is an important one in digital communication. Alteras programmable gate array (FPGA), design of parallel mechanism based on high level data link control (HDLC) Protocol control system. The system uses a combination of modular design method, complex combination of features from the various modules of the system implementation, this block makes the design is clear and easy to modify. The system effectively uses the FPGAs internal hardware resources, enabling parallel multi-channel HDLC protocol message generation and parsing. Through an analysis of the current implementation of HDLC Protocol General, pointed out that there are some drawbacks, have come up with a hardware processing of the HDLC protocol using FPGA programming methods and verification on FPGA implementation of HDLC protocol using FPGA programming methods and verification on FPGA implementation of HDLC protocol frame sequence-a cyclic redundancy check (CRC) explains. Module downloaded to the hardware test passed, confirm the feasibility of FPGA implementation of HDLC Protocol, application module programming simple and easy to modify so that it has a lot of advantages. In data communication in order to reduce the error rate of the transmission of communication lines, requires the use of high-efficiency error control method. Cyclic redundancy check CRC as the coding is simple and effective, is one of the most common channel coding. 【Key words】HDLC protocol FPGA CRC check 目录 前言………………………………………………………………