FPGA设计及应用_VHDL4.pptVIP

FPGA设计及应用 有限状态机设计技术 用状态机描述的优点 状态机的基本概念 Moore型： 状态机的输出仅与状态机的状态有关，与状态机的输入无关 Mealy型： 状态机的输出由状态机的输入和状态机的状态共同决定 VHDL状态机设计步骤 2. 主控时钟进程设计 process(reset,clk) begin if reset=‘1’ then current_state=初始状态; elsif clk’event and clk=‘1’ then current_state=next_state; end if; end process; 3.主控组合进程设计 process(current_state,其他输入信号) begin case current_state is when state1= output=xxx; …. Next_state=某个状态 when state2= output=xxx; … ….. End case; end process; MOORE 状态机设计 ARCHITECTURE behave OF moore_exaple IS TYPE state_type IS (s0, s1, s2,s3);---状态定义 SIGNAL current_state,next_state: state_type; BEGIN Switch_to_next_state:PROCESS (clk,reset) BEGIN IF reset = 1 THEN current_state = s0; ELSIF clkEVENT AND clk = 1 THEN current_state=next_state; END IF; END PROCESS; MOORE 状态机设计(续) Change_state:PROCESS (current_state,datain) CASE current_state IS WHEN s0 = IF datain=1 THEN next_state = s1; else next_state =s0; END IF; dataout=“0001”; WHEN s1 =IF datain=‘0 THEN next_state = s2; else next_state =s1; END IF; dataout=“0010”; WHEN s2 = IF datain=1 THEN next_state = s3; else next_state =s2; END IF; dataout=“0100”; WHEN s3 = IF datain=‘0 THEN next_state = s0; else next_state =s3; END IF; dataout=“1000”; end caes; end process; MEALY 状态机设计 Change_state:PROCESS (current_state,datain) CASE current_state IS WHEN s0 =IF datain=1 THEN next_state = s1; else next_state =s0; END IF; if datain=‘1’; then dataout=“0001”; els