FPGA设计及应用_VHDL3.pptVIP

带使能端的BCD-7段译码器 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity decoder48 is port(adr : in std_logic_vector(3 downto 0); en : in std_logic; decodeout: out std_logic_vector(6downto 0) ); end decoder48; architecture behave of decoder48 is begin process(en,adr) begin if en=‘0’ then decodeout=“0000000’; else case adr is when “0000’=decodeout=“1111110”; when“0001’=decodeout=“0110000”; ……. when others=decodeout=“1111011”; end case; end if; end process;end behave; 优先编码器 library ieee; use ieee.std_logic_1164.all; entity encoder is port(a,b,c,d,e,f,g,h : in std_logic; codeout : out std_logic_vector(2 downto 0) ); end encoder; architecture behave of encoder is begin codeout=111 when h=1 else 110 when g=1 else 101 when f=1 else 100 when e=1 else 011 when d=1 else 010 when c=1 else 001 when b=1 else 000 when a=1 else 000 ; end behave; 移位寄存器 library ieee; use ieee.std_logic_1164.all; ENTITY shifter IS PORT (data :in std_logic_vector(7 downto 0); sl_in,sr_in,reset,clk: IN std_logic; mode :in std_logic_vector(1 downto 0); qout : buffer std_logic_vector(7 downto 0)); END shifter; 移位寄存器 ARCHITECTURE behave OF shifter IS BEGIN PROCESS (clk) BEGIN IF (clkEVENT AND clk = 1) THEN if(reset=1) then qout=(others=0); --同步清零 else case mode is when 01= qout=sr_in qout(7 downto 1); --右移 when 10= qout=qout(6 downto 0) sl_in; --左移 when 11= qout=data; --置数 when others=null; --“NULL”表示无操作 end case; end if; END IF; END PROCESS; END behave; 三态输出电路表示法1 library ieee; use ieee.std_logic_1164.all; entity triout is port (data_in :in std_logi