典型组合逻辑集成电路资料.ppt

//Behavioral description of 2-to-1-line multiplexer module mux2to1_bh(A, B, SEL, L); input A, B, SEL; output L; reg L; //define register variable always @(SEL or A or B) if (SEL == 1) L = b; //也可以写成 if (SEL) L=B; else L = A; endmodule 例 //Behavioral description of 4-to-1-line multiplexer module mux4to1_bh(A,SEL,E,L); input [3:0] A; input [1:0] SEL; output L; reg L; always @(A or SEL or E) begin if (E==1) L = 0; else case (SEL) 2’d0: L = A[0]; 2’d1: L = A[1]; 2’d2: L = A[2]; 2’d3: L = A[3]; endcase end endmodule