lecture10_ASM.ppt

Algorithmic State MachinesSortingSigned Unsigned Data Types Sources Required Reading Algorithmic State Machine Algorithmic State Machine – representation of a Finite State Machine suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables. Elements used in ASM charts (1) Elements used in ASM charts (2) State box – represents a state. Equivalent to a node in a state diagram or a row in a state table. Moore type outputs are listed inside of the box. It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z=1. Also, it might be useful to write an action to be taken, e.g., Count = Count + 1, and only later translate it to asserting a control signal that causes a given action to take place. Elements used in ASM charts (3) Decision box – indicates that a given condition is to be tested and the exit path is to be chosen accordingly The condition expression consists of one or more inputs to the FSM. Conditional output box – denotes output signals that are of the Mealy type. The condition that determines whether such outputs are generated is specified in the decision box. ASM Chart for Mealy FSM – Example 2 ASM Chart for Control Unit - Example 3 Pseudocode for the sort operation Datapath Circuit for the sort operation Control Circuit – Part 1 VHDL code (1) – Entity declaration LIBRARY ieee; USE ieee.std_logic_1164.all; USE ponents.all ; ENTITY sort IS GENERIC ( N : INTEGER := 4 ) ; PORT (Clock, Resetn : IN STD_LOGIC ; s, WrInit, Rd : IN STD_LOGIC ; DataIn : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; RAdd : IN INTEGER RANGE 0 TO 3 ; DataOut : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Done : BUFFER STD_LOGIC ) ; END sort ; Package components (1) Package components (2) Datapath Circuit for the sort operation VHDL code (2) – Datapath signal declarations ARCHITECTURE Dataflow OF sort IS -- datapath data buses TYPE RegArr