湘潭大學本部2011级EDA作业答案.docxVIP

答案由个人做出，可能有不全或错误之处，欢迎大家批评指正。2.3什么是重载函数？重载算符有何用处？如何调用重载算符函数？同样名称的函数可以用不同的数据类型作为此函数的参数定义多次，以此定义的函数称为重载函数。被重载的运算符能够对新的数据类型进行操作，或者允许不同的数据类型之间用此运算符进行运算。按重载运算符的方式严格调用重载算符函数2.15图2.18中的f_adder是一位全加器，cin是输入进位，cout是输出进位，试给输出的电路的VHDL描述。library ieee;use ieee.std_logic_1164.all; entity ff is port (x,y,clock:in std_logic; sum:out std_logic); end; architecture one of ff is component f_adder port(a,b,ci:in std_logic; su,co:out std_logic); end component; component df port(d,cl:in std_logic; q1:out std_logic); end component; signal cout,tmp:std_logic; begin u1:f_adder port map(a=x,b=y,ci=tmp,su=sum,co=cout); u2:df port map(d=cout,cl=clock,q1=tmp); end architecture one;library ieee;use ieee.std_logic_1164.all; entity df is port (d,cl:in std_logic; q1:out std_logic); end; architecture two of df is signal qq:std_logic; begin process(cl,qq) begin if cl event and cl=1 then qq=d; end if; end process; q1=qq; end architecture two;library ieee;use ieee.std_logic_1164.all; entity f_adder is port (a,b,ci:in std_logic; su,co:out std_logic); end; architecture three of f_adder is component h_adder port(a1,b1:in std_logic; so,cou:out std_logic); end component; component or2a port(a1,b1:in std_logic; c:out std_logic); end component; signal d,e,f:std_logic; begin u1:h_adder port map(a1=a,b1=b,cou=d,so=e); u2:h_adder port map(a1=e,b1=ci,cou=f,so=su); u3:or2a port map(a1=d,b1=f,c=co); end architecture three;library ieee;use ieee.std_logic_1164.all; entity h_adder is port (a1,b1:in std_logic; so,cou:out std_logic); end; architecture four of h_adder is begin so=not(a1 xor(not b1)); cou=a1 and b1; end architecture four;library ieee;use ieee.std_logic_1164.all; entity or2a is port (a1,b1:in std_logic; c:out std_logic); end; architecture five of or2a is begin c=a1 or b1; end architecture five;2.29用VHDL设计实现一百进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt100 is port(clk,rst,en:in std_logic; cq:out std_logic_vector(6 downto 0); cout:out std_logic);end cnt100;architectu