本科毕业论文---ldo线性稳压器设计.docVIP

LDO线性稳压器设计毕业论文 摘 要 随着电源管理IC技术的不断发展，高性能低成本的电源管理芯片越来越受到用户的青睐。LDO线性稳压器以其低噪声、高电源抑制比、微功耗和简单的外围电路结构等优点而被广泛应用于各种直流稳压电路中。为适应电源市场发展的需要，结合LDO系统自身特点，设计了一款低功耗、高稳定性LDO线性稳压器。 本文首先简要介绍了LDO线性稳压器的工作原理与基本性能指标。其次，从瞬态、直流、交流三方面对系统结构进行深入研究，阐述LDO稳压器的设计要点与各种参数的折衷关系。随后从低功耗设计的角度出发，对各子模块结构进行优化，从而确立最终的系统架构。通过建立LDO电路的交流小信号模型，计算得到系统的环路增益并由此推出电路中零极点的分布位置从而获得研究系统稳定性问题的途径。针对文中采用的两级级联误差放大器直接驱动调整管栅极的拓扑结构，引入嵌套式密勒补偿和动态零点补偿两种方法来保证系统的稳定性要求。讨论了嵌套式密勒补偿中调零电阻可能存在的位置，确定最合适的补偿结构从而有效地消除了右半平面零点对系统稳定性的影响。最后分析了各子模块电路的结构与工作原理，并给出了LDO系统模块与整体仿真的结果与分析。 电路设计采用了CSMC 0.6um CMOS工艺模型，对LDO稳压器在不同的模型、输入电压、温度组合下进行前仿真验证。结果表明：电路不带负载的静态电流为1.79 uA，系统带宽几乎不随负载变化，在输出电流范围内能保证较好的稳定性。 关键词：线性稳压器，低压差，嵌套式密勒补偿，动态零点补偿，低功耗 Abstract With rapid development of power IC technology, high performance low cost power management chips become more and more popular. LDO linear regulator is widely used in various kinds of DC regulating voltage circuits, for the benefits of low noise, high power supply rejection ratio (PSRR), micro power loss, and simple peripheral structure etc. In order to meet the needs of power market development, combining with self features of LDO system, this thesis proposes a kind of LDO linear regulator with low power and excellent stability. Firstly, this thesis gives a brief introduction on working principles and basic indicators of LDO regulator. System structure will be deeply discussed in TRAN, DC, AC three aspects and designing key points along with various parameter trade-off relationships will be expounded subsequently. Then, optimums every sub-module and determines the final system architecture from the angle of low power design. In order to obtain the path to research on stability of LDO system, calculates loop gain and deduces zero-pole distribution by setting up AC small signal models. Nested miller compensation (NMC) and Tracking-frequency compensation will be introduced to ensure the stability of LDO topological structure which adopts two stage cascade error amplifier driving pass element directly. Discusses