controlunitoperation课程.pptVIP

William Stallings Computer Organization and Architecture6th Edition Chapter 16 Control Unit Operation 控制器的操作 ※§16.1 Micro-Operations 微操作 A computer executes a program 计算机执行程序 —Fetch/execute cycle —取指/执行周期 Each cycle has a number of steps Called micro-operations —μops 每个周期都要执行一系列的步骤—称为微操作 see chapter 12 information flow见12章信息流 Each step does very little 每一步都只是做很少操作 Atomic(基本的或原子的) operation of CPU 是CPU最基本的操作 Constituent Elements of Program Execution 程序执行的构成元素 Four Registers 四个寄存器 They are essential to instruction execution 它们对指令的执行很重要 Memory Address Register (MAR) 存储器地址寄存器 — Connected to address bus 连接到地址总线 — Specifies address for read or write in memory — 指出对进行读写操作的存储器的地址 Memory Buffer Register (MBR)存储器缓冲寄存器 — Connected to data bus 连接到数据总线 — Holds data to write to or read from memory —保存对存储器读写操作的数据 Program Counter (PC) 程序计数器 — Hold address of next instruction to be fetched — 保存要取的下条指令的地址 Instruction Register (IR) 指令寄存器 — Hold the last instruction fetched — 保存刚取的最后一条指令 1. Fetch Sequence 取指的操作序列 Address of next instruction is in PC 下条指令的地址在PC中 Address (MAR) is placed on address bus 地址（MAR寄存器中）放到地址总线上 Control unit issues READ command 控制单元发出存储器读命令 Result (data from memory) appears on data bus 结果（从存储器获取的数据）出现在数据总线上 Data from data bus copied into MBR 从数据总线上获得的数据拷贝到MBR PC incremented by 1 (in parallel with data fetch from memory) PC内容加1（可以和从存储器获取数据并行进行） Data (instruction) moved from MBR to IR 数据（指令）从MBR传送到IR MBR is now free for further data fetches MBR寄存器现在释放了，已经可以接着（用来）取数据了 See page422 figure12.6 Information Flow (Fetch Diagram) Fetch Sequence (symbolic) t1: MAR - (PC) 书上不详细，参考 t2: MBR - (memory) PC - (PC) +1 t3: IR - (MBR) (tx = time unit/clock cycle) or t1: MAR - (PC) t2: MBR - (memory) t3: PC - (PC) +1 IR - (MBR) Fetch –T1 Fetch –T2 Fetch –T3 Fetch –T4 Fetch Sequence (symbolic) t1: (PC) - MAR t2: (MAR) Memory by address bus read Memory by c