VLSIArchitecturesforIterativeDecoders学习课件.pptVIP

Outline Architectural Objectives for Iterative Decoders Speed 1Gbps Minimal control logic. Minimal memory requirement through reuse of storage elements. SRAMs without address decoding. TURBO DECODERS Unrolled Iterative Decoder MAP Decoders (BCJR) Windowed MAP Algorithm MAP Decoder: Block Architecture Partitioning of Branch Metric Memory SOVA: Implementation [Berrou93] Structure for a 4-State SOVA Implementation (Register Exchange Method) Decoders for Low Density Parity Check Codes (LDPC) LDPC: Overview LDPC Operations Pipelined Architecture of LDPC Decoder Comparison of SISO Decoders Summar