VHDL门级与结构建模学习课件.pptVIP

#5 s=2‘b00; // 加载选择信号s[1:0] $display($time, “ d=%b, s[1]=%b, s[0]=%b, out=%b \n”,d,s[1],s[0],out); //延时后显示结果 #5 s=2b01; $display($time, “ d=%b, s[1]=%b, s[0]=%b, out=%b \n,d,s[1],s[0],out); #5 s=2b10; $display $time, (“ d=%b, s[1]=%b, s[0]=%b, out=%b \n,d,s[1],s[0],out); #5 s=2b11; $display($time, “ d=%b, s[1]=%b, s[0]=%b, out=%b \n,d,s[1],s[0],out); end endmodule 4选1多路选择器测试模块1仿真结果 run -all # 0 d=1010, s[1]=0, s[0]=0, out=x # 5 d=10