FPGA Prototyping By Verilog Examples第六章 状态机FSMD设计.docxVIP

FSMD(带数据通道的有限状态机)是FSM和常规时序电路的结合。基于RT methodology的消抖电路设计本设计中主要的数据通道是一个用户自定制的21位递减计数器，其作用为：1：可初始化为一个指定的值；2：具有递减计数和暂停计数的功能；3：当计数器计数为0的时候，输出一个状态信号。module debounce_explicit ( input wire clk, reset, input wire sw, output reg db_level, db_tick ); // symbolic state declaration localparam [1:0] zero = 2b00, wait0 = 2b01, one = 2b10, wait1 = 2b11; // number of counter bits (2^N * 20ns = 40ms) localparam N=21; // signal declaration reg [1:0] state_reg, state_next; reg [N-1:0] q_reg; wire [N-1:0] q_next; wire q_zero; reg q_load, q_dec;//q_load:load the initial value;q_dec:enable the counter // body // fsmd state data registers always @(posedge clk, posedge reset) if (reset) begin state_reg = zero; q_reg = 0; end else begin state_reg = state_next; q_reg = q_next; end // FSMD data path (counter) next-state logic assign q_next = (q_load) ? {N{1b1}} : // load 1..1 (q_dec) ? q_reg - 1 :// decrement q_reg; // status signal assign q_zero = (q_next==0); // FSMD control path next-state logic always @* begin state_next = state_reg; // default state: the same q_load = 1b0; // default output: 0 q_dec = 1b0; // default output: 0 db_tick = 1b0; // default output: 0 case (state_reg) zero: begin db_level = 1b0; if (sw) begin state_next = wait1; q_load = 1b1; end end wait1: begin db_level = 1b0; if (sw) begin q_dec = 1b1; if (q_zero) begin state_next = one; db_tick = 1b1; end end else // sw==0 state_next = zero; end one: begin db_level = 1b1; if (~sw) begin state_next = wait0; q_load = 1b1; end end wait0: begin db_level = 1b1; if (~sw) begin q_dec = 1b1; if (q_zero) state_next = zero; end else // sw==1 state_next = one; end default: state_next = zero; endcase endendmodule另一种可替代的代码风格:将RT(寄存器传输)的操作嵌入到FSM控制通路中，我们不需要明确的指定数据通路的元素，只需要在相应的FSM状态中列出RT操作即可。// Listing 6.2module debounce ( input wire clk, reset, input wire sw, output reg db_level, db_tick ); // symbolic state declaration localparam [1:0] zero = 2b00, wait0 = 2b01, one = 2b10, wait1 = 2b11; // number