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A Practical Implementation Of Silicon Microchannel Coolers
Evan G. Colgan, R. J. Bezama, Michael Gaynes and Kenneth C. MarstonIBM Corporation
IntroductionMore than twenty-five years ago, Tuckerman and Pease first described the use of silicon microchannel cooling for very high power densities [1]. However, the coolers could not be fabricated easily and pressure drops were very high. As chip power densities are now increasing beyond air cooling limits, a variety of liquid cooling methods are being investigated. Due to the high heat transfer coefficient associated with it, microchannel cooling is an attractive approach, but several practical issues need to be addressed. Reviews of microchannel cooling are available [2-4], though only a few recent publications discuss integration of microchannel coolers with packaged silicon chips [5-9]. In previous work [7-9], we addressed some of the practical issues for implementing silicon microchannel cooling in a single chip module (SCM).
Silicon Microchannel DesignRecent progress in high-rate, deep reactive ion etching (DRIE) of Si [10] has greatly simplified the fabrication of silicon microchannel coolers. Also, methods for reducing the pressure drop have been reported including subdividing the flow into multiple heat exchanger zones with shorter channel lengths [11] and manifold designs with large cross-sectional area (i.e. equal, or larger than, the channel cross-sectional area) [12].
?A 3-D rendering of part of an assembled microchannel cooler is shown in Figure 1, where the manifold chip is on top and is shown as semi-transparent green. In operation, alternate zigzagged rows of fluid vias are used as inlets and outlets, so the 20 x 20 mm microchannel cooler is divided into six parallel-fed heat exchanger zones and the flow length between the inlets and outlets is about 3 mm. The fluid vias in the manifold chip were formed as zigzagged arrays of circular openings instead of elongated slots to reduce the likelihood of the
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