8位十进制频率计数器.docVIP

主程序 library ieee; use ieee.std_logic_1164.all; entity A is port ( clk:in std_logic; fsin:I in std_logic; carry_out2:out std_logic; dout: out std_logic_vector(31 downto 0)); end A; architecture invq of A is component testctl port(clk: in std_logic; tsten:out std_logic; clr_cnt: out std_logic; load: out std_logic); end component; component cnt10 port(clk,clr,ena: in std_logic; cq:out std_logic_vector(3 downto 0); carry_out: out std_logic); end component; component reg16b port(load:in std_logic; din:in st