2016年调研报告.pptVIP

3D-TSV 测试调研报告 马鹤 2011/8/13 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 3D stacked ICs To address the ever increasing need for low cost, high density devices a new industry design paradigm has emerged. 3D stacked IC (SIC) using Through Silicon Via (TSV) interconnects offers the opportunity to integrate multiple ICs at lower cost and silicon footprint than conventional System in Package (SiP) technologies. Due to the new advanced manufacturing processes and physical access limitations of the TSVs, it is necessary for us to know the new characterizations of the TSVs. Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. Test Content Electrical Characterization of 3D TSV Ⅰ、TSV DC characterization Ⅱ、AC characterization Ⅲ、High frequency characterization Equivalent thermal conductivity of TSV Test for 3D chips Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. Ⅰ、DC Characterization A. TSV resistance For an accurate measurement of TSV resistance, 4-point Kelvin resistor configurations are adopted Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. DC Characterization isolated TSVs show some voids or interfaces between the TSV and the landing pad, which are affecting the TSV contact resistance. This problem is absent in the dense TSV structures; causes are still under investigation. Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. DC Characterization B. TSV yield TSV matrix structures where each TSV in the array is accessible for electrical measurement have been implemented. Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0