lec17multiplexeradder.pptVIP

Parity-Checking Applications 用于检测代码在传输和存储过程中是否出现差错 A EVEN ODD 74x280 H I A EVEN ODD 74x280 H I 发 端 收 端 DB[0:7] DB[0:7] ERROR 发端保证有偶数个1 收端 ODD 有效表示出错 奇数 EVEN */41 6.10 Adder (加法器) Half Adder （半加器） 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 A B S CO (半加器真值表) Sum (相加的和): S = A’·B + A·B’ = A ? B Carry (向高位的进位)： CO = A·B Truth Table of Half Adder Half adder propagation delays tadd = 3 tgate tcarry = 2 tgate */41 S CO X Y CI S = X ? Y ? CI 0 0 1 0 0 1 1 1 CI XY 00 01 11 10 0 1 CO CO=X·Y+X·CI+Y·CI = X·Y+(X+Y)·CI 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 CI X Y S CO 全加器真值表 Full Adder（全加器） Truth Table of Full Adder Full adder propagation delays tadd = 3 tgate tcarry = 2 tgate */41 Ripple Adder (串行进位加法器) X Y CI CO S X Y CI CO S X Y CI CO S X Y CI CO S C1 C2 C3 C4 C0 S0 S1 S2 S3 X0 Y0 X1 Y1 X2 Y2 X3 Y3 =0 回顾：串行比较器 —— Improve Speed: Parallel Adder Ripple-Carry Adder (n-bits) tadd = (n - 1)2 tgate + 3 tgate = (2n + 1) tgate Cascaded Multi-bit Adder */41 X Y CI CO S X Y CI CO S X Y CI CO S X Y CI CO S C1 C2 C3 C4 C0 S0 S1 S2 S3 X0 Y0 X1 Y1 X2 Y2 X3 Y3 X Y CMP EQI EQO X0 Y0 X1 Y1 XN-1 YN-1 EQ1 EQ2 EQN EQN-1 1 X Y CMP EQI EQO X Y CMP EQI EQO An Iterative Comparator Ripple Adder Primary Inputs Primary Outputs Boundary Inputs Boundary Outputs 级联输出 */41 一位全加器：S = X ? Y ? Ci Ci+1 = X·Y + (X+Y)·Ci Carry-Look ahead Adder(先行进位加法器) Carry lookahead (先行进位法)：第 i 位的进位输入信号可以由该位以前的各位状态决定。 Ci+1 = (Xi·Yi) + (Xi+Yi)· Ci = Gi + Pi · Ci Carry generate 进位产生信号 Carry propagate 进位传递信号 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Ci X Y S Ci+1 全加器真值表 */41 先行进位法：第 i 位的进位输入信号可以由该位以前的各位状态决定。 C0 = 0 Ci+1 = Gi + Pi · Ci C0 = 0 C1 = G0+P0·C0