CH2_INTRODUCTIONCH2_INTRODUCTION.docVIP

Part one GENERAL INTRODUCTION The 8051 is the original member of the MCS-51 family, and is the core for all MCS-51 devices. The features of the 8051 core are：l 8-bit CPU optimized for control applications Extensive Boolean processing (Single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually addressable I/O lines Two 16-bit timer/counters Full duplex UART(Universal Asynchronous Receiver Transmitter) 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator Part two BASIC ARCHITECTURAL STRUCTURE The basic architectural structure of this 8051 core is shown in Figure 1:  Part Three HARDWARE DESCRIPTION 8051, 8052 AND 80C51 HARDWARE DESCRIPTION INTRODUCTION Part Four Special Function Registers A map of the on-chip memory area called SFR (Special Function Register)space is shown in Figure2. SFRS marked by parentheses are resident in the 8052s but not in the 8051s. Note that not all of the addresses are occupied. Unoccupied address areas are not implemented on the chip. Read access to these addresses will in general return random data and write accesses will have no effect. User software should not write 1s to these unimplemented locations, since they may be used in future MCS-51 products to invoke new features. In that case the reset or inactive values of the new bits will always be 0, and their active values will be 1. The functions of the SFRS are outlined below. ACCUMULATOR ACC is the Accumulator register. The mnemonics for Accumulator-Specific instructions, however, refer to the Accumulator simply as A. B REGISTER The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register. PROGRAM STATUS WORD The PSW register contains program status information. STACK POINTER The Stack Pointer Register