PCI接口时序测试方法.docVIP

PCI 接口时序测试方法 参考文献: Intel(R) I/O Controller Hub 4 (ICH4) External Design Specification(EDS). (No.589) PCI SPECIFICATION V2.2. 测试目的: 在P4D项目(Springdale-G/PE)中, 主要看PCI接口的PCICLK,AD 和C/BE#[3,0]等控制信号的时序质量是否满足规范要求. 测试内容和规范 特别说明:时序测试中PCI接口的参考电平的值为Vtest=-1.5v(对5V环境的PCI卡): The following is refer to ICH4. Table 19-10. PCI Interface Timing Sym Parameter Min Max Units Notes Figure t40 AD［31;0］ Valid Delay 2 11 ns Min: 0pF Max: 50pF 19-3 t41 AD［31:0］ Setup Time to PCICLK Rising 7 ns 19-4 t42 AD［31:0］ Hold Time from PCICLK Rising 0 ns 19-4 t43 C/BE［3:0］#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK# DEVSEL# Valid Delay from PCICLK Rising, 2 11 ns Min: 0pF Max: 50pF 19-3 t44 C/BE［3:0］#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK# IDSEL, DEVSEL# Output Enable Delay from PCICLK Rising, 2 ns 19-7 t45 C/BE［3:0］#, FRAME#, TRDY#, IRDY#, STOP#, PERR#, PLOCK# DEVSEL#, GNT［A:B］# Float Delay from PCICLK Rising, 2 28 ns 19-5 t46 C/BE［3:0］#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, Setup Time to PCICLK Rising, 7 ns 19-4 t47 C/BE［3:0］#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR# DEVSEL#, REQ［A:B］# Hold Time from PCICLK Rising, 0 ns 19-4 t48 PCIRST# Low Pulse Width 1 ms 19-6 t49 GNT［A:B］#, GNT［5:0］# Valid Delay from PCICLK Rising 2 12 ns t50 REQ［A:B］#, REQ［5:0］# Setup Timer to PCICLK Rising 12 ns The following is refer to PCI spec2.2. 7.6.4.2 Timing Parameters Table 7-4: 66MHz and 33 MHz Timing Parameters 66MHz 33MHz7 Symbol Parameter Min Max Min Max Units Notes Tval CLK to Signal Valid Delay-bused signals 2 6 2 11 ns 1,2,3,8, Tval(ptp) CLK to Signal Valid Delay-point to point signals 2 6 2 12 ns 1,2,3,8 Ton Float to Active Delay 2 2 ns 1,8,9 Toff Active to Float Delay 14 28 ns 1,9, Tsu Input Setup Time to CLK-bused signals 3 7 ns 3,4,10 Tsu(ptp) Input Setup Time to CLK-point to point signals 5 10,12 ns 3,4 Th Input Hold Time form CLK 0 0 ns 4 Trst Reset Active Time after power stable 1 1 ms 5 Trst