ProcedureControl-Analog-Sim-and-CoSim-Caselists.docVIP

Analog IP Simulation Case-lists and Co-sim Case lists Project Project Manager Analog IP Block Name Analog Designer Design Complete Date Final Design Review Date Approved by Approval Date  Index 1 Lists of Analog IP Simulation Cases 3 2 List of Analog IP co-sim cases 5  Lists of Analog IP Simulation Cases Based on the requirements of project specifications, the project manager and/or the top-level analog front-end designer must give the simulation case-lists and the simulation result analysis report for all analog IPs, the simulation case-lists must cover all the kinds of conditions in reality with all Process-Voltage-Temperature corner combinations. (1).The followings list all the process-voltage-temperature combination of corners that all analog IP must be simulated. All PVT-Corner Combinations MOS: tt/ff/ss/sf/fs Bipolar: tt_bip/ff_bip/ss_bip Resistor: tt_res/ff_res/ss_res Capacitor: tt_cap/ff_cap/ss_cap Supply Voltage: Vdd ± 20% Temperature: -40℃ ～ 125℃ Variations of External resistors, capacitors or bias current：±10%～±20% (2).The floowings list the general simulations that all analog IP must be simulated: Simulation Cases DC saturation check All the key MOS devices (such as current mirrors or bias circuits etc) must operate in the saturation region,. Requirement: Vdsat≥100mV；Vds/Vdsat≥1.5 DC mismatch check All the key analog IPs (such as current mirrors or differential-input Op-Amp) must check the influence of device mismatch by Monte-Carlo simulation or hand-calculation based on the process mismatch model DC current check All the analog IPs must check the DC current (power) consumptions under the normal condition and the power-down leakage current. AC stablity check If negative feedback exists, must check its small-signal ac stability (such as gain, phase margin, unity gain frequency etc). Requirements: minimal phase margin≥50(for pre-sim) or 45(for post-sim); minimal gain margin≥10dB Transient stability check If neg