数字电路的FPGA设计与实现（基础篇）教学课件作者刘岚附件6-7课件.docVIP

【附件6-7】 module uartr(reset,clock, s_in, data_out, rdsig, parity_error, framing_error); input reset; input clock; //采样时钟 input s_in; //UART数据输入 output[7:0]data_out; //接收数据输出 output rdsig; output parity_error; //资料出错指示 output framing_error; //帧出错指示 reg[7:0] data_out; reg rdsig; reg parity_error; reg framing_error; reg [7:0] control_cnt; reg rxbuf, rxfall, receive; parameter paritymode = 1b0; reg parity, idle; always @(posedge clock) begin rxbuf = s_in; rxfa