Closing the Power Gap between ASIC and Custom关闭ASIC和习俗之间的权力差距.ppt

Closing the Power Gap between ASIC and Custom David Chinnery, Kurt Keutzer Outline Motivation for focusing on reducing ASIC power The power gap between ASIC and custom Where does the power go? What can we do about it? Conclusions on automating low power techniques Why power? Battery life is limited by power (e.g. laptop, mobile phone) Cost for packaging and cooling increase rapidly with power dissipation (e.g. plastic vs. ceramic package, heatsink, fan) Higher temperatures degrade performance and reliability Circuits are slower, with more leakage, at higher temperature Less reliable due to increased rate of electromigration Increasing integration increases power demand in portable applications (e.g. mp3 player/PDA/mobile phone combined) Performance is limited by power now even for high end microprocessors Power of high performance chips has increased As device dimensions (W, L, Tox) scaled down by a factor k, for high performance, If supply Vdd and threshold voltage Vth fixed, then power/unit area ? k3 If Vdd and Vth scaled downlinearly and , then power/unit area ? k0.7 Further voltage scaling may be limited … Impact of voltage scaling on power Major components of power: Ptotal = Pdynamic + Pleakage Dynamic power due to switching of capacitances Reducing Vdd gives quadratic reduction in Pdynamic But transistor drive current depends on Vdd Must reduce Vth to maintain drive current But reducing Vth increases subthreshold leakage current, which is the major contributor to Pleakage Must look for other ways to reduce power Automate low power techniques Custom designers can try to optimize the design at all levels Electronic design automation (EDA) tools for ASICs Most of the design optimization is high level Fast time-to-market and lower design cost Increasingly important to reduce design cost for larger chips What is the power gap between (automated) ASIC design and custom design? We need to characterize the contributi