EDA技术实用教程(第二版)潘松黄继业第2版第8章_VHDL结构与要素课件教学.pptVIP

BEGIN u1 : NoteTabs PORT MAP (clk=CLK8HZ, ToneIndex=ToneIndex); u2 : ToneTaba PORT MAP (Index=ToneIndex,Tone=Tone,CODE=CODE1,HIGH=HIGH1); u3 : Speakera PORT MAP(clk=CLK12MHZ,Tone=Tone, SpkS=SPKOUT ); END; 【例8-31】 LIBRARY IEEE; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Speakera IS 接下页 PORT ( clk : IN STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END; ARCHITECTURE one OF Speakera IS SIGNAL PreCLK, FullSpkS : STD_LOGIC; BEGIN DivideCLK : PROCESS(clk) VARIABLE Count4 : STD_LOGI