FPGA设计-ADC0809.docxVIP

目录摘要21设计任务42系统设计原理42.1 硬件设计原理42.1.1 ADC0809的主要特性42.1.2 ADC0809的外部特性42.1.3工作过程52.2 软件设计思路62.3 程序流程图73功能与时序仿真83.1 功能仿真得出的RTL图83.2 功能仿真得出的状态图83.3 时序仿真94总结95参考文献10附录一 程序11摘要实现时必须严格遵守ADC0809的工作时序，对选定的通道输入一个模拟量，调节电位器改变输入的模拟量。利用quartus2进行文本编辑输入和试仿?；给出仿真波形。最后进行引脚锁定并进行测试，硬件验证ADC0809?的控制功能。具体过程为：编写ADC0809时序的VHDL代码。对其进行编译仿真主要控制信号为：Start为转换启动信号，高电平有效；ale为通道选择地址信号的锁存信号。当启动转换后，程序开始执行，查询状态，状态为0.1.时等待，状态2时，查询EOC信号的状态，判断是否转换结束，当EOC=1时表示转换结束，否则继续等待；转换结束后继续查询状态，若OE信号为高电平则控制打开三态缓冲器，当LOCK信号为高电平时，将转换后的数据进行锁存，至此一次转换结束。关键词：工作时序、AD0809?、VHDL、quartus2、编译仿真、Start?、EOC、OE、三态缓冲器AbstractImplementation must strictly abide by the work timing of ADC0809, an analogue for the selected channel input, adjust the potentiometer change the analog input. Using quartus2 to input text editing and try copy; The simulation waveform is given. Finally pin lock and test, the control function of the hardware validation ADC0809. Concrete process is: the timing of ADC0809 VHDL code.To compile the simulation main control signal is: Start for conversion Start signal, high efficient;Ale for channel selection address signal is latched signals. , when start the conversion, program starts executing the query status, the status of 0.1. While waiting, state 2, track the status of EOC signal, judge whether the conversion is over, when the EOC = 1 said switch over, or continue to wait for; Transformation after the end of continue to query the state, if the OE signal for high level control to open the tri-state buffer, when the LOCK signal for high electricity at ordinary times, the converted data latches, ended a transformation.Keywords: Work timing、AD0809?、VHDL、quartus2、Compile the simulation、Start?、EOC、OE、Tri-state buffer1设计任务基于VHDL语言，实现对ADC0809简单控制。2系统设计原理2.1 硬件设计原理ADC0809?为单极性输入,8位转换逐次逼近A/D转换器,可对0～5V的INT0～INT7的8路模拟电压信号分时进行转换,完成一次转换的时间为100?微秒。ADD-CBA作为8路通道选择地址,在转换开始前由地址锁存允许信号ALE将3位地址锁入锁存器中,以确定转换信号通道；EOC为状态结束标志,低电平转为高电平时转换结束；START为转换启动信号,上升沿有效;OE为数据输出允许端,高电平有效;〔D0?D7〕为A/D变换数据输出端。本次实验为测试方便，因此直接选择IN0端口为输入端，即使ADDC，ADDB，ADDA都接地