[计算机专业英语电子教案PPT第2章.ppt

Computer English Chapter 2 Organization of Computers 2.4 I/O Subsystem Organization and Interfacing The load logic plays the role of the enable logic in the input device interface. When this logic receives the correct address and control signals, it asserts the LD signal of the register, causing it to read data from the systems data bus. The output device can then read the data from the register at its leisure while the CPU performs other tasks. 装载逻辑发挥着输入设备接口中使能逻辑的作用。当此逻辑获得正确的地址信号和控制信号后，它发出寄存器的LD信号，促使它从系统数据总线上读取数据。然后输出设备可以在其空闲的时候从寄存器中读取该数据，同时CPU可以执行其他的任务。 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 2.4 I/O Subsystem Organization and Interfacing A variant of this design replaces the register with tri-state buffers. The same logic used to load the register is used to enable the tri-state buffers instead. Although this can work for some designs, the output device must read in data while the buffers are enabled. Once they are disabled, the outputs of the buffers are tri-stated and the data is no longer available to the output device. 该设计也可以用三态缓冲器代替寄存器。装载寄存器的逻辑同样用于使能三态缓冲器。虽然对于某些设计这是可行的，但是输出设备必须在缓冲器有效时读入数据。一旦缓冲器被禁止，其输出就是三态，该数据也就不再能够供输出设备使用。 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 2.4 I/O Subsystem Organization and Interfacing Some devices are used for both input and output. A personal computers hard disk drive falls into this category. Such a device requires a combined interface that is essentially two interfaces, one for input and the other for output. Some logic elements, such as the gates that check the address on the address bus, can be used to generate both the buffer enable and regi