(精)VHDL语法应用——最新.pptVIP

13、VHDL语言的库文件 library IEEE; use IEEE.numeric_bit.all; entity Adder4_v2 is port(A, B: in unsigned(3 downto 0); Ci: in bit; -- 输入 S: out unsigned(3 downto 0); Co: out bit); -- 输出 end Adder4_v2; architecture overload of Adder4_v2 is signal Sum5: unsigned(4 downto 0); begin Sum5 = 0 A + B + unsigned(0=Ci); -- 加法器 S = Sum5(3 downto 0); Co = Sum5(4); end overload; 无符号矢量4位加法器的VHDL程序 13、VHDL语言的库文件 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Adder4_v3 is port(A, B: in std_logic_vector(3 downto 0); Ci: in std_logic; --输入 S: out std_logic_vector(3 downto 0); Co: out std_logic); --输出 end Adder4_v3; architecture overload of Adder4_v3 is signal Sum5: std_logic_vector(4 downto 0); begin Sum5 = 0 A + B + Ci; --adder S = Sum5(3 downto 0); Co = Sum5(4); end overload; 14、用VHDL进程模拟寄存器和计数器 process(CLK) begin if CLK’event and CLK = ‘1’ then Q1 = Q3 after 5 ns; Q2 = Q1 after 5 ns; Q3 = Q2 after 5 ns; end if ; end process; process(CLK) begin if CLK’event and CLK = ‘1’ then if CLR = ‘1’ then Q = “0000”; elsif Ld = ‘1’ then Q = D; end if ; end if; end process; 14、用VHDL进程模拟寄存器和计数器 process(CLK) begin if CLK’event and CLK = ‘1’ then if CLR = ‘1’ then Q = “0000”; elsif Ld = ‘1’ then Q = D; elsif LS = ‘1’ then Q = Q(2 downto 0) Rin; end if ; end if; end process; signal Q: unsigned (3 downto 0); process(CLK) begin if CLK’event and CLK = ‘1’ then if ClrN = ‘0’ then Q = “0000”; elsif En = ‘1’ then Q = Q+1; end if ; end if; end process; 14、用VHDL进程模拟寄存器和计数器 library IEEE; use IEEE.numeric_bit.all; entity c74163 is port(LdN, ClrN, P, T, Clk: in bit; D: in unsigned(3 downto 0); Cout: out bit; Qout: out unsigned(3 downto 0)); end c74163; architecture b74163 of c74163 is signal Q: unsigned(3 downto 0); -- Q is the counter register begin Qout = Q; Cout = Q(3) and Q(2) and Q(1) and Q(0) and T;