PT_S13的W1_07.pptVIP

Agenda: Day Two Unit Objectives State why physical data is useful during top-level integration State what is SDF data State the three parasitic models PrimeTime accepts State the precedence of back-annotated data Why Use Physical Data? Timing Convergence The goal is to achieve timing convergence with the physical tools Without timing convergence, there may be many iterations between the logical and physical tools before timing closure! Execute top-level integration with available physical data Prelayout, timing analysis performed based on wire load models Postlayout, replace wire load models with actual net parasitic data The Limitation of Wire Load Models The “Cost” of Estimating Net Delays In large geometries, net delay was only a small portion of a path’s total delay Estimating the timing of a “low impact” portion of the circuit is OK In smaller geometries, delays due to net capacitance are a large portion of the path delay Introduction to Physical Data Parasitic versus SDF SDF back-annotation is used to describe net and cell delays No cell or net delay calculation by PT - a “frozen” snapshot Parasitic back-annotation is used to describe net resistance and capacitance (RC). RCs are used for Performing design rule analysis (for example, max_capacitance) Computation of cell and net delays if no SDF is annotated Using SDF will be faster than delay calculation with parasitics For multiple analyses on the same netlist, use PT to generate SDF for subsequent runs report_timing with Physical Data Back-Annotation Command Summary read_sdf report_annotated_delay, report_annotated_check remove_annotated_delay, remove_annotated_check read_parasitics report_annotated_parasitics remove_annotated_parasitics Parasitic Back-Annotation Different Parasitic Formats set_load/set_resistance -- Lumped RC Model SPEF -- Standard Parasitic Exchange Format (IEEE standard) RSPF -- Reduced Standard Parasitic Format DSPF -- Detailed Standard Parasitic Format Lumped RC Data More o