可編程逻辑器件的实验程序.docVIP

LS04 非门 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY FM04 IS PORT(A : IN STD_LOGIC ; Y : OUT STD_LOGIC ); END ; ARCHITECTURE bhv OF FM04 IS BEGIN PROCESS (A) BEGIN IF A = 1 THEN Y=0; ELSE Y=1; END IF; END PROCESS ; END ARCHITECTURE bhv; LS08 与门 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY YM08 IS PORT ( A, B : IN BIT; Y : OUT BIT ); END ENTITY YM08; ARCHITECTURE one OF YM08 IS BEGIN PROCESS (A,B) BEGIN IF A=1 AND B=1 THEN Y=1; ELSE Y = 0 ; END IF; END PROCESS; END ARCHITECTURE one ;