LEB an Vertex 2001 Trip report.pptVIP

G.Chiodini - Oct 15, 2001 - Fermilab LEB and Vertex 2001 Trip report Gabriele Chiodini Fermilab, October 15, 2001 – Monday pixel meeting Attended conferences 7th Workshop on Electronics for LHC Experiments. Stockholm, Sweden, 10-14 Sep. 2001. Plenary sessions: Partially depleted SOI; Trends: DSM, FPGA, and PCB. LHC status; electronics for Cal, Pix and AMS in space. Hera-B commissioning. Parallel sessions: Tracker FE –Trigger electronics B+Rad effs –Cal electronics Optoelec. -DAQ and DCS Muons FE -GND+cooling+align. How to win a Nobel price!!! 10th International workshop on vertex detectors. Brunnen, Switzerland 23-28 Sep. 2001. Only plenary sessions: Operating vertex Planned vertex Sensors Detector readout Triggering with vertex Hybridization and monolithic Other applications LEB01: Partially depleted SOI (K. Bernstein - IBM) QM limitation to scaling law requires new concepts : PD SOI , DTMOS, FinFET, … ------------------------------- Floating body effect in SOI. PD SOI operation mode: equilibrium, dynamic, steady. Delay: spatial + temporal. Advantages: Less C (eSIMOX = 4.1, eSi = 12). Lower threshold. No Latch-up. Applications: SRAM, powerPC, … Very few analog circuit in SOI. Trend in industry(1) Scaling in DSM (K. Bernstein-IBM): Now tox= 0.1 um (0.25 um is 4 generation beyond ). Scaling limitation due to QM (Roll-off from Morthy’s law if not innovation). Problems: Process spread (yield), power and temperature distribution, electromigration, hot carriers, SEU from surrounding material, oxide scaling (5 atoms, Igate is an issue), interconnect capacitive coupling, V drop. Innovation: Device : DP SOI, FinFeT, Strained Si MOSFET. Package: Chip Stack Module, 3D neural network. System: Compiler and multiprocessor parallelism (it’s the future:no monster chip). PC board (J.Bovier- Creative Electronic System) Strong demand from new chip and technology: BGA and FBGA, fast dynamic, multi PS, good cooling, low EMI. New board require a high level designs (no c