ASIC esign flow.pptVIP

ASIC Design Overview Pete Fiacco Vice President, ASIC Development Emulex My Background Designed, architected or managed more than 40 chips. 90nm, 130nm, 0.18u, 0.25u, 0.35u, 0.50u CMOS IBM, LSI Logic, VLSI Technology (Phillips), Motorola, National Semiconductor, Toshiba, Chip Express, Quick Logic, Xilinx, Altera and others Millions of logic gates, dozens of embedded memories, speeds to 4 Ghz, multiple embedded RISC processors, complex packages, complex I/O interfaces BSEE. Cal Poly, Pomona. 1984 MSEE. CSUF, USC, UCLA, UCI 1991 My Company Emulex Market technology leader in SAN (Storage Area Networking) Recently named one of the 25 Fastest-Growing Technology Companies by Forbes Products based on ANSI Fibre Channel IEEE Ethernet Technology ~ 400 employees world-wide Over $320M annual revenue Types of Chips in Use Today Full Custom Designed at the transistor level. Every transistor is optimized Custom packages Highly process technology- dependent Standard- Cell (ASIC) Designed at the gate (cell) level Cell library is pre-characterized Gate Array (ASIC) Like Standard-cell, except only interconnect is customized FPGA Like Gate-Array Logic blocks are programmable, generic bigger Interconnect is programmable Typical ASIC Design Flow Top Down- Create a Design Spec Create A Top-Level Block Diagram Emulex ASIC Semiconductor Overview ASIC Fabrication Partners LSI Logic Standard Cell IBM Microelectronics Standard Cell Quicklogic, Xilinx FPGA Design Rules CMOS Std Cell 0.09u, 4/5LM, 1.2 V Core CMOS Std Cell 0.13u, 4/5LM, 1.8/2.0 V Core CMOS Std Cell 0.18u, 4/5LM, 2.5 V Core Packaging EPBGA Flip-Chip ASIC Tools Overview Cadence NC-Verilog NCSim Logic Simulators Avanti Hspice Analog Simulators Cadence SignalScan GUI Avanti VeriLint, Verisity SureLint Syntax/Code Checkers Cadence Coverscan Verilog Code Coverage Tools Synopsys Design Complier Expert/Analyzer Logic Synthesis Synopsys Design Time PrimeTime Static Timing Analysis Mentor FastScan- IScan Synthesis ATPG L