单片机原理及应用第六讲_MSP430F5XX6XX的时钟模块(UCS)实验报告.docVIP

单片机原理及应用 实验报告 报告人： 实验内容 ACLK = REFO = 32.768kHz, MCLK = SMCLK =Default 1MHz 实验2 时钟设置实例 ACLK = REFO = 32kHz, MCLK = SMCLK =8MHz 实验ACLK = REFO = 32kHz, MCLK = SMCLK =12MHz 实验ACLK = REFO = 32kHz, MCLK = SMCLK =20MHz 实验步骤 ： (1) PC 和板载仿真器通过USB 线相连； (2) 打开CCS 集成开发工具，选择样例工程或自己新建一个工程，修改代码 (3) 选择对该工程进行编译链接，生成.out 文件。然后选择，将程序下载到实验板中。程序下载完毕之后，可以选择全速运行程序，也可以选择单步调试程序，选择F3 查看具体函数。也可以程序下载之后，按下，软件界面恢复到原编辑程序的画面。再按下实验板的复位键，运 行程序。（调试方式下的全速运行和直接上电运行程序在时序有少许差别，建议 上电运行程序）。 关键代码： Main(){ WDTCTL = WDTPW+WDTHOLD; // Stop WDT P4DIR |= BIT1; // P4.1 output P1DIR |= BIT0; // ACLK set out to pins P1SEL |= BIT0; P3DIR |= BIT4; // SMCLK set out to pins P3SEL |= BIT4; while(1) { P4OUT ^= BIT1; __delay_cycles(60000); // Delay } 实验2： #include msp430.h int main(void){ volatile unsigned int i; WDTCTL = WDTPW+WDTHOLD; // Stop WDT P4DIR |= BIT1; // P1.1 output P1DIR |= BIT0; // ACLK set out to pins P1SEL |= BIT0; P3DIR |= BIT4; // SMCLK set out to pins P3SEL |= BIT4; UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx // Loop until XT1,XT2 DCO stabilizes ‐ In this case only DCO has to stabilize do { UCSCTL7 = ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 = ~OFIFG; // Clear fault flags }while (SFRIFG1OFIFG); // Test oscillator fault flag __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation UCSCTL2 |= 249; // Set DCO Multiplier for 8MHz // (N + 1) * FLLRef = Fdco, (249 + 1) * 32768 = 8MHz __bic_SR_register(SCG0); // Enable the FLL control loop // Worst‐case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx UG for // optimization , 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle __delay_cycles(250000); while(1) { P4OUT ^= BIT1; // Toggle P1.1 __delay_cycles(600000); // Delay } } 实验3： #include msp430.h int