第3章+组合逻辑电路设计.pptVIP

Chapter 3 - Part 1 * Verification Example: Simulation Simulation procedure: Use a schematic editor or text editor to enter a gate level representation of the final circuit Use a waveform editor or text editor to enter a test consisting of a sequence of input combinations to be applied to the circuit This test should guarantee the correctness of the circuit if the simulated responses to it are correct Short of applying all possible “care” input combinations, generation of such a test can be difficult Chapter 3 - Part 1 * Verification Example: Simulation Enter BCD-to-Excess-3 Code Converter Circuit Schematic AOI symbolnot available Chapter 3 - Part 1 * Verification Example: Simulation Enter waveform that applies all possible input combinations: Are all BCD input combinations present? (Low is a 0 and high is a one) Chapter 3 - Part 1 * Verification Example: Simulation Run the simulation of the circuit for 120 ns Do the simulation output combinations match the original truth table? Chapter 3 - Part 1 * Terms of Use All (or portions) of this material ? 2008 by Pearson Education, Inc. Permission is given to incorporate this material or adaptations thereof into classroom presentations and handouts to instructors in courses adopting the latest edition of Logic and Computer Design Fundamentals as the course textbook. These materials or adaptations thereof are not to be sold or otherwise offered for consideration. This Terms of Use slide or page is to be included within the original materials or any adaptations thereof. Chapter 3 - Part 1 * Design Example Specification BCD to Excess-3 code converter Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word Implementation: multiple-level circ