verilog培训教程文件.pptVIP

* * Microelectronics School Xidian University wire [DATA_WIDTH-1:0] x1,y1,z1; wire [DATA_WIDTH-1:0] x2,y2,z2; wire [DATA_WIDTH-1:0] x3,y3,z3; wire [DATA_WIDTH-1:0] x4,y4,z4; wire [DATA_WIDTH-1:0] x5,y5,z5; wire [DATA_WIDTH-1:0] x6,y6,z6; wire [DATA_WIDTH-1:0] x7,y7,z7; reg [1:0] quadrant[PIPELINE:0]; integer i; //get real quadrant and map to first quadrant always@(posedge clk or negedge rst_n) begin if(!rst_n) phase_in_reg=8b0000_0000; else if(ena