基于FPGA的数字频率计的设计.doc

课 程 设 计 说 明 书 课程设计名称： EDA技术课程设计 题 目： 数字频率计电路设计 学 生 姓 名： 指 导 教 师： 卿 朝 进 日期：2011年5月 30日 摘要: 频率计具有数字频率计是直接用十进制来显示被测信号频率的一种测量装置。本设计用Verilog HDL在CPLD器件上实现数字频率计测频系统，能够用十进制数码显示被测信号的频率，能够测量正弦波、方波、三角波等信号的频率，而且还能对其他多种物理量进行测量。具有体积小、可靠性高、功耗低的特点。数字频率计是计算机、通讯设备、音频视频等科研生产领域不可缺少的测量仪器。基于测频原理及FPGA的设计思想,给出了一种新型数字测频系统的设计方案,系统采用Verilog HDL语言,运用自顶向下的设计思想,采取将系统按功能逐层分割的层次化设计方法。在具体实现上,以FPGA为中央处理器对被测频率信号进行周期采样,通过调用Quartus II的宏功能模块进行占空比计算。 关键词：FPGA芯片、Verilog HDL语言、数字频率计、数字频率计原理图、Quartus II软件。 Abstract: The frequency meter with digital frequency meter is directly in the decimal to display the measured signal of the frequency of a measuring instrument. This design in CPLD device with Verilog HDL on its digital frequency meter frequency measurement system, to be able to use the decimal digital display measured the frequency of the signal, able to measure the sine wave, square wave, triangle wave and the frequency of the signal, but also to other a variety of physical quantity measurement. The advantages of small size, high reliability, low power consumption characteristics. Digital frequency plan is a computer, communication equipment, audio video in scientific research production field indispensable measuring instrument. Based on frequency measurement principle and FPGA design thought, this paper presents a new digital frequency measurement system, the design of the system Verilog HDL language, using the top-down design thought, system function will take according to the division of the step by step a hierarchical design method. In the specific implementation, with FPGA for central processor to be measured frequency signal sampling period, by calling the macro Quartus II module occupies emptiescompared calculation. Keywords: the FPGA chip, Verilog HDL language, digital cymometer, the digital cymometer account principle diagram and Quartus II software. 目录 1、EDA技术的介绍和发展 3 1.1EDA技术的介绍 3 1.2 EDA技术的发展 3 1.3 EDA技术的发展趋势 4 2