产业化基地扶持所在地的集成电路设计单位.pptVIP

DAC 2003 Recent Research Progresses in Zhejiang University Xiaolang Yan Outline Introduction Design For Manufacture Formal Verification SoC and Platform Design Introduction Recent RD Activities Research in the ICSOC framework Research supported by various funding RD in joint labs with Samsung and National Semiconductor Industrial co-operations Recent Educational Activities A series of short courses given by 8 professors from U.S., in IC training center in Hangzhou Joint master and Ph.D. programs with Royal Institute of Technology, Sweden (KTH) Design For Manufacture Lithographic Modeling New OPC Methods Full-Chip PSM Processing Tool Manufacturing Pattern Verification DFM of Standard Cells New Processes Development Lithographic Modeling New Test Structure Generation Tool Script-driven automatic layout generation Testing for various physical settings Prepared for fine model characterization 130nm, 90nm Lithographic Model Fitting Well-matched results with measurements obtained Content-Driven OPC Method Content-Driven Dissection and Correction Processing emphasis is put on functional parts such as channels New Dissection Method for Frugal OPC Distortion is measured as one criterion for edge dissection Full-chip PSM processing Phase Shifter Insertion and Phase Assignment on Full Chip Level Red/Blue: phase shifter with 0/180 phases Sub-100nm Standard Cell Designs Sub-100nm Standard Cell DFM Flow and Real Design Cases Trial OPC, trial PSM steps are added in the design flow Lithographic simulation is performed to analyze the manufacturability of designed cells in different environment settings Cells are being verified in test circuitries on test chips. A 90nm DFF designed with good manufacturability Test patterns zoomed-in Cells and testing circuitries Tape-out Formal Verification Verification-Oriented Synthesis Combinational Equivalence Checking Sequential Equivalence Checking with Retimed Circuits Integrated Arithmetic Verific