19,20现代CMOS工艺基本流程(英文).pptVIP

* 2nd through Nth Interconnect Layer Pattern Photoresist for Metal2 Interconnects: Adjacent metal layers are patterned perpendicular to each other to minimize inductive coupling between layers (not shown in cross-sectional diagram). Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Source N+ Drain P+ Source P+ Drain BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 Photoresist * 2nd through Nth Interconnect Layer Etch Metal2: An RIE etch utilizing chlorine chemistry. Multiple etch steps are required due to the multiple different metal layers. Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Source N+ Drain P+ Source P+ Drain BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 Photoresist * 2nd through Nth Interconnect Layer Strip Photoresist: 2nd interconnect layer is completed. Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Source N+ Drain P+ Source P+ Drain BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 * 8.Passivation Deposit Passivation Layer: There are many types of passivation (silicon nitride, silicon oxynitride, polyimide, and others). Its purpose is to protect the completed circuit from scratches, contamination, and moisture. Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Source N+ Drain P+ Source P+ Drain BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 Passivation * Passivation Pattern Passivation Layer: Polyimide passivation is photo-definable. Other passivation layers require a patterned photoresist layer followed by an etch step. Bond pad openings allow electrical access to the chip. Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Source N+ Drain P+ Source P+ Drain BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 Passivation Bond Pad Poly Gate Gate Oxide Silicide Spacer * Review of CMOS Cross Section Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Source N+ Drain P+ Source P+ Drain BPSG W Contact Plug Metal 1