ECE 331 – Digital System DesignECE 331–数字系统设计.pptVIP

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ECE 331 – Digital System DesignECE 331–数字系统设计.ppt

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* * * * * * * * * * * * * * * * * * * * * * * * ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #11) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning. Fall 2010 ECE 331 - Digital System Design * The Half Adder (HA) Fall 2010 ECE 331 - Digital System Design * The Half Adder 0 0 1 1 + 0 + 1 + 0 + 1 0 1 1 10 Sum Carry Sum Fall 2010 ECE 331 - Digital System Design * The Half Adder A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Truth Table Fall 2010 ECE 331 - Digital System Design * The Half Adder Exercise: 1. Derive the Boolean expressions for the sum and the carry outputs. 2. Draw the associated combinational logic circuit diagrams. Fall 2010 ECE 331 - Digital System Design * The Full Adder (FA) Fall 2010 ECE 331 - Digital System Design * The Full Adder 0 0 0 0 0 0 1 1 + 0 + 1 + 0 + 1 0 1 1 10 Carry-out Sum 1 1 1 1 0 0 1 1 + 0 + 1 + 0 + 1 1 10 10 11 Carry-in Fall 2010 ECE 331 - Digital System Design * The Full Adder A B Cin Sum Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Truth Table Fall 2010 ECE 331 - Digital System Design * The Full Adder Exercise: 1. Derive the Boolean expressions for the sum and the carry outputs. 2. Draw the associated combinational logic circuit diagrams. Fall 2010 ECE 331 - Digital System Design * The Full Adder Exercise: Design a Full Adder using 2 Half Adders 1 OR gate Fall 2010 ECE 331 - Digital System Design * The Full Adder Half Adder Half Adder A B Cin Sum Cout Fall 2010 ECE 331 - Digital System Design * More VHDL Fundamentals Fall 2010 ECE 331 - Digital System Design * VHDL: Components Specify the logical sub-circuits (i.e. components) that will be used in a hierarch