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Efficient Storage of Defect Maps for Nanoscale Memory
Susmit Biswas
Tzvetan S. Metodi*
Frederic T. Chong
Ryan Kastner
Tim Sherwood
{susmit,chong,sherwood}@cs.ucsb.edu,
kastner@ece.ucsb.edu, tsmetodiev@ucdavis.edu
*
April 16, 2017
Nanotechnology in Action
Scaling limit of CMOS
Vdd ~ 1V
Leakage
Design of new nanoscale devices
SONOS, CMOL, Crossbar memories
CNT interconnect
April 16, 2017
Nanotechnology: Pros and Cons
Higher Density
5nm=Fnano = 10nm
Faster operation
Fast switching
Low active power
Inexpensive
Reliability
Manufacturing defects might be as high as 10% [DeHon-NanoTech2005]
April 16, 2017
Solution: Reconfiguration
Dynamic
High latency in testing
Static: Defect Map
Using bit-level reconfiguration
High overhead in storage
Block level reconfiguration
Efficient storage techniques !
April 16, 2017
Presentation overview
Motivation
Prior Work
Our Approach
Algorithms
Results
Conclusion
April 16, 2017
Prior Work
1D list of regions [sun-NanoArch-06]
Bloom filter defect map [Wang-ICCAD2006]
April 16, 2017
Example: A Defective Memory
April 16, 2017
Map of good regions
List based approach
Ranges
1D
2D
Can be stored in TCAM
Good for correlated defects
April 16, 2017
Storing Defect Map in Rectangles
April 16, 2017
Equivalent Problem:Finding optimal rectangle cover
NP-Complete problem
Greedy Algorithm
R-Tree as data structure
New point inserted greedily for least increase in rectangle area
Suitable for storing ranges
k-means clustering to decide the insertion order of points
April 16, 2017
Algorithm
April 16, 2017
Algorithm 1: Illustration
R3
R4
R5
R6
Root
R2
R1
April 16, 2017
Storing Sparse Defect Locations
Bloom filter defect map [Wang-ICCAD2006]
Supports membership queries
Uniform hash function
No false negative
False positive
Better storage efficiency than bit vector
0
1
0
1
0
0
1
0
0
1
H2 (d1)
H1(d1)
H3 (d1)
H4 (d1)
D={d1, d2,…, dn}
April 16, 2017
Bloom filter as Defect Map
m/n
fp
2
0.393
3
0.237
4
0.147
5
0.092
6
0.0561
7
0.0347
8
0.0216
9
0.0133
10
0.00819
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