状态机实现位乘法器.docVIP

状态机实现 16 位乘法器 一：状态机实现16位乘法器的源程序: module fsm_mult16(mux, pmux, clk, reset, out, mid, done); input[15:0] mux,pmux; input clk, reset; output[31:0] out, mid; output done; reg[31:0] out, mid; reg done; integer count; reg[1:0] pstate, nstate; parameter idle=2b00, add=2b01, shift=2b10; always @(posedge clk) if(!reset) begin pstate=idle; end else begin pstate=nstate; end always @(pstate or reset) begin nstate=idle; case(pstate) idle: begin out=0; done=0; count=0; mid[15:0]=mux; mid[31:16]=16b0; nstate=add; end add: begin if(pmux[count]) out=out+mid; nstate=shift; end shift: begin count=count+1; mid={mid[30:0],1b0}; if(count==16) begin nstate=idle; done=1; end else nstate=add; end default: nstate=idle; endcase end endmodule 二：状态机实现16位乘法器的测试代码： `timescale 1ns/1ns `include fsm_mult16.v module fsm_mult16_test; reg clk, reset; reg[15:0] mux, pmux; wire[31:0] out; wire done; wire[31:0] mid; fsm_mult16 mod1(mux, pmux, clk, reset, out, mid, done); initial begin clk=0; reset=0; mux=16b1101_0101_0101_0101; pmux=16b1111_1111_1111_1111; #5 reset=1; #1000 $finish; end always #10 clk=~clk; initial $monitor($time,,,%d*%d=%d,mux, pmux,out); endmodule 三：Transcript显示结果： # Reading D:/altera/91/m