HDS服务器产品技术回顾及市场定位.pptVIP

The QPI interconnects at the top of this diagram depict that each processor is directly connected to every other processor in the merged blade set. Therefore the maximum memory latency is a single processor hop if the data requested resides in a memory bank that is directly connected to a different processor than the requesting one. This is a NUMA memory scheme but the default memory scheme is SMP. This can be changed for each blade via the blade management browser interface. The physical processor set can be configured in a variety of ways Dedicated cores, shared cores and core groupings.