VHDL逻辑设计.pptVIP

VHDL邏輯設計 題目：４＿１０解碼器 姓名：李國豪 學號：目標 　將四個ＢＣＤ輸入訊號解碼成十個ＬＥＤ顯示０～９十進制電路 真值表 當I(3,)I(2),I(1),I(0)輸入為 ”0 0 0 0 “ , 則輸出O(0)~O(9)為 ”1000000000” 當I(3,)I(2),I(1),I(0)輸入為” 0 0 0 1 “ , 則輸出O(0)~O(9)為 ”0100000000” 當I(3,)I(2),I(1),I(0)輸入為” 0 0 1 0 “ , 則輸出O(0)~O(9)為 ”0010000000” 當I(3,)I(2),I(1),I(0)輸入為” 0 0 1 1 “ , 則輸出O(0)~O(9)為 ”0001000000” 當I(3,)I(2),I(1),I(0)輸入為” 0 1 0 0 “ , 則輸出O(0)~O(9)為 ”0000100000” 當I(3,)I(2),I(1),I(0)輸入為” 0 1 0 1 “ , 則輸出O(0)~O(9)為 ”0000010000” 當I(3,)I(2),I(1),I(0)輸入為” 0 1 1 0 “ , 則輸出O(0)~O(9)為 ”0000001000” 當I(3,)I(2),I(1),I(0)輸入為” 0 1 1 1 “ , 則輸出O(0)~O(9)為 ”0000000100” 當I(3,)I(