CMOS集成电路闩锁效应形成机理和对抗措施.docVIP

目 录 TOC \o 1-4 \h \z \u HYPERLINK \l _Toc261023959 摘 要： PAGEREF _Toc261023959 \h 1 HYPERLINK \l _Toc261023960 0 前言 PAGEREF _Toc261023960 \h 1 HYPERLINK \l _Toc261023961 1 闩锁效应产生背景 PAGEREF _Toc261023961 \h 2 HYPERLINK \l _Toc261023962 2 CMOS反相器 PAGEREF _Toc261023962 \h 3 HYPERLINK \l _Toc261023963 2.1 反相器电路原理 PAGEREF _Toc261023963 \h 3 HYPERLINK \l _Toc261023964 2.2反相器工艺结构 PAGEREF _Toc261023964 \h 3 HYPERLINK \l _Toc261023965 3 闩锁效应基本原理 PAGEREF _Toc261023965 \h 4 HYPERLINK \l _Toc261023966 3.1 闩锁效应简介 PAGEREF _Toc261023966 \h 4 HYPERLINK \l _Toc261023967 3.2 闩锁效应机理研究 PAGEREF _Toc261023967 \h 4 HYPERLINK \l _Toc261023968 3.3 闩锁效应触发方式 PAGEREF _Toc261023968 \h 6 HYPERLINK \l _Toc261023969 4 闩锁措施研究 PAGEREF _Toc261023969 \h 6 HYPERLINK \l _Toc261023970 4.1 版图级抗栓所措施 PAGEREF _Toc261023970 \h 6 HYPERLINK \l _Toc261023971 4.2 工艺级抗闩锁措施 7 HYPERLINK \l _Toc261023972 4.3 电路应用级抗闩锁措施 9 HYPERLINK \l _Toc261023973 5 结论 9 HYPERLINK \l _Toc261023974 参考文献: 10 CMOS集成电路闩锁效应形成机理和对抗措施 摘 要： CMOS Scaling理论下器件特征尺寸越来越小，这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应，这种寄生的双极晶体管一旦被外界条件触发，会在电源与地之间形成大电流通路，导致器件失效。闩锁效应已成为CMOS集成电路在实际应用中主要失效的原因之一。 本文以反相器电路为，介绍了CM0S集成电路的工艺结构；采用双端PNPN结构模型．较为详细地分析了CM0S电路闩锁效应的形成机理；给出了产生闩锁效应的必要条件与闩锁的触发方式，介绍了在电路版图级、工艺级和电路应用时如何采用各种有效的技术手段来避免、降低或消除闩锁的形成，这是CMOS集成电路得到广泛应用的根本保障。 关键词： CM0S集成电路；闩锁效应；功耗；双端pnpn结；可控硅 Study on the mechanism of Latch-up effect in CMOS IC and its countermeasures Wangxin Abstract: Device channel length become more and more short under CMOS Scaling,such that latch-up effect in CMOS structure is stand out increasingly．Latch—up is a parasitic effect in CMOS circuits．Once the parasitic BJT is triggered,there will be high current from VDD to GND，which makes the chip invalidation． Latch—up phenomenon become the main reason of CMOS IC applied． Based on inverter，the structure of CMOS IC are presented ,The model of pnpn diodeis took to analyze the mechanism of Latch—up effect in CMOS IC． The necessary conditions and the trigger mo