数字系统设计与EDA技术第2版作者于润伟第6章VHDL语言的顺序语句课案.pptVIP

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SPCOUNT IS PORT( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce, load, dir : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR (3 DOWNTO 0); Q : BUFFER STD_LOGIC_VECTOR (3 DOWNTO 0)); END SPCOUNT; ARCHITECTURE A OF SPCOUNT IS BEGIN PROCESS(clk,reset) VARIABLE counter: STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN IF reset=1 THEN counter:=0000; -- reset高电平有效 ELSIF clkEVENT AND clk=1THEN IF load=1THEN counter:=din; ELSE IF ce=1 THEN IF d