数字设计基础双语教学版作者英BarryWilknson双语课件（第12章）课案.pptVIP

* 12. Describe sequential systems in VHDL 12.1 Defining clocks, flip-flops and registers 12.2 Register Transfer Level (RTL) Coding 12.3 Sequential logic 12.1 Defining clocks, flip-flops registers 1. Defining a clock signal PROCESS BEGIN clock = ‘0’; WAIT FOR 10 NS; clock = ‘1’ WAIT FOR 10 NS; END PROCESS; There are many ways to define a clock. For example: Simulation waveform 12.1 Defining clocks, flip-flops registers 2. The D-type flip-flop LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff IS PORT ( d, clock: IN STD_LOGIC; Q: OUT