EDA第五章VHDL设计进阶4-8节-子程序以后-定稿讲述.ppt

LIBRARY IEEE; II、 8-3线优先编码器 例5-45 方法1 USE IEEE.STD_LOGIC_1164.ALL; --使用条件赋值语句实现 ENTITY encoder IS PORT( a,b,c,d,e,f,g,h:IN STD_LOGIC; out0,out1,out2:OUT STD_LOGIC); END encoder; ARCHITECTURE behave1 OF encoder IS --条件赋值方式 SIGNAL outvec:STD_LOGIC_VECTOR(2 WOWNTO 0); BEGIN outvec(2 DOWNTO 0)= “111”WHEN h=‘1’ ELSE “110”WHEN g=‘1’ ELSE “101”WHEN f=‘1’ ELSE “100”WHEN e=‘1’ ELSE “011”WHEN d=‘1’ ELSE “010”WHEN c=‘1’ ELSE “001”WHEN b=‘1’ ELSE “000”WHEN a=‘1’ ELSE “000”; out0 = outvec(0); out1 = outvec(1); out2 = outvec(2); END behave1; LIBRARY IEEE; -- 8-3线优先编码器 例5-45 方法2 USE IEEE.STD_LOGIC_1164.ALL; --使用LOOP语句实现 USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY encoder IS PORT( a,b,c,d,e,f,g,h:IN STD_LOGIC; out0,out1,out2:OUT STD_LOGIC); END encoder; ARCHITECTURE behave2 OF encoder IS BEGIN PROCESS(a,b,c,d,e,f,g,h) VARIABLE inputs:STD_LOGIC_VECTOR(7 DOWNTO 0)； VARIABLE i:INTEGER; BEGIN inputs:=(h,g,f,e,d,c,b,a);--使用位置关联法 i:=7; WHILE i0 AND inputs(i)/=‘1’ LOOP—找到第一个inputs(i)=‘1’ i:=i-1; END LOOP; (out2,out1,out0)=CONV_STD_LOGIC_VECTOR(i,3); END PROCESS;--将整形i转化为3位标准逻辑矢量类型赋给端口 END behave2; LIBRARY IEEE; -- 8-3线优先编码器 例5-45 方法3 USE IEEE.STD_LOGIC_1164.ALL; --使用IF语句实现 ENTITY encoder IS PORT( in1:IN STD_LOGIC_VECTOR(7 DOWNTO 0); out1:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END encoder; ARCHITECTURE behave3 OF encoder IS BEGIN PROCESS(in1) BEGIN IF in1(7)=‘1’ THEN out1=“111”;--注意优先级 ELSIF in1(6)=‘1’ THEN out1=“110”; ELSIF in1(5)=‘1’ THEN out1=“101”; ELSIF in1(4)=‘1’ THEN out1=“100”; ELSIF in1(3)=‘1’ THEN out1=“011”; ELSIF in1(2)=‘1’ THEN out1=“010”; ELSIF in1(1)=‘1’ THEN out1=“001”; ELSIF in1(0)=‘1’ THEN out