Niagara a 32Way Multithreaded SPARC Processor尼亚加拉瀑布32多线程SPARC处理器.pptVIP

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Niagara a 32Way Multithreaded SPARC Processor尼亚加拉瀑布32多线程SPARC处理器.ppt

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Niagara a 32Way Multithreaded SPARC Processor尼亚加拉瀑布32多线程SPARC处理器

Niagara: a 32-Way Multithreaded SPARC Processor P. Kongetira, K. Aingaran, K.Olokotun Sun Microsystems Goal Commercial server applications: High thread level parallelism (TLP) Large numbers of parallel client requests Low instruction level parallelism (ILP) High cache miss rates Many unpredictable branches Frequent load-load dependencies Power, cooling, and space are major concerns for data centers Sun’s Solution UltraSPARC T1 processor “the highest-throughput and most eco-responsible processor ever created”? Multicore Fine-grain multithreading within core Simple pipelines Small L1 cache Shared L2 Metric: Performance/Watt Architecture Sparc pipe UltraSPARC II style Single issue 6 stage: F, S, D, E, M, W Shared units: L1 $ TLB X units pipe registers Integer Register file One register file / thread SPARC window: in, out, local registers Highly integrated cell structure to support 4 threads: 8 windows of 32 locations / thread 3 read ports + 2 write ports Read/write: single cycle latency 1 Active Window Cell (copy of the architectural set window) Thread scheduling Thread selection based on: Previous long latency instruction in pipe Instruction type LRU status Select Fetch coupled Memory 16 KB 4 way set assoc. I$/ core 8 KB 4 way set assoc. D$/ core 3MB 12 way set assoc. L2 $ shared 4 x 750KB independent banks 2 cycle throughput, 8 cycle latency Direct link to DRAM Jbus Manages cache coherence for the 8 cores CAM based directory Performance “Home run“ ? Relatively slow single-thread performance Poor floating-point performance Lack of software support ( Sun Fire T2000 does not support Linux or Windows) Price Concurrency counterattack no place as a general-purpose computer running databases small low-end market segment ? Niagara II The “Rock” – multiprocessor enhanced single thread support References [1] P. Kongetira, et al, “A 32-Way Multithreaded SPARC Processor,” IEEE Micro, vol. 25, pp. 21-29, Mar., 2005. [2] A. S. Leon, et al, “A Power-Efficient Hi